Silicon Navigator has developed key components for digital design that operate on the OpenAccess database and utilize the RDE Framework foundation. These solutions are targeted at cell based design starting at RTL, or even pre-RTL, and extending into the implementation flow for floorplanning, place&route, and optimization. These solutions can directly import Verilog RTL or synthesized netlists. Analysis is performed using Liberty (Synopsys .lib) models for timing, power and leakage. Physical data is provided via models in LEF, DEF and GDSII. RTL Elaboration and Processing Silicon Navigator's Verilog RTL module can import the full System Verilog, Verilog 2001, and Verilog languages. Synthesizable subsets of these can be elaborated and mapped to generic gates or directly onto a Liberty/LEF described target library. Companies like AMIS use the RTL processing for FPGA to ASIC mapping and chip implementation. The system has very fast turnaround time making it ideal for estimation and early analysis. RDA (RTL and Design Analysis) RDA is a system for analysis of imported netlists or elaborated RTL. It provides the engines to incrementally display schematics generated from a netlist and enable connectivity tracing in the design hierarchy. Additionally it provides the means to perform clock, set/reset and test discovery. Used with the static timing engine, it is capable of performing clock relationship data-mining to create SDC and clock relationships. Power and Leakage Analysis Power Analysis can be performed directly from RTL or mapped netlists. RTL is elaborated or netlists are imported into a target library which is described in the Liberty format for power and timing. Liberty (Synopsys .lib format) provides the required models to analyze leakage and active power. For power analysis, parasitic data for the routing can be automatically estimated, provided via wire-load models or extracted from placed or routed data. Power is calculated using transition density switching probabilities starting from a complete or partial SAIF (Synopsys Switching Activity Interface File). Switching activity is generated for all nodes by probability and power results are produced. Analysis of total or module power is provided along with leakage power. Process corners are supported by using multiple Liberty files. Static Timing Analysis Silicon Navigator has extended the OpenAccess database model to support static timing analysis using Liberty timing models and SDC timing constraints. Initially, full timing is performed and the incremental mode of operation initialized. Under incremental timing any changes like gate sizing, buffer insertion, parasitic changes, or an ECO can be quickly analyzed in a incremental fashion with the use of observers. The timing verification, budgeting, and ILM creation all are layered into the OpenAccess EMH occurrence model. Floorplaning Services Silicon Navigator has a large number of floorplanning and physical design engines integrated into RDE on OpenAccess. These engines can be used from early floorplanning all the way to custom design. Services available from Silicon Navigator are incremental static timing analysis with optimization, floorplan initialization and optimization, amoeba hierarchy display, congestion analysis and display, hierarchy re-partitioning, pin-optimization, placement, and buffering. Large Capacity The efficient implementation and the underlying OpenAccess database allow RDE to manage designs of 2-million place-able cells in a 32-bit operating system (more when the available 64-bit version is used). Final routed GDS files of over 14 gigabytes have been displayed and edited. High performance is achieved in the RDE digital environment by incremental operation utilizing incremental engines and OpenAccess observers. Simple gate changes can be reflected in timing results within a few seconds, even when accounting for physical effects.